Core i7にTLBのエラッタが発覚？！

・Nehalem also has a TLB bug - Fudzilla

・Intel Core i7 Processor Extreme Edition Series and Intel Core i7 Processor - Intel(英語/PDF)

Core i7にTLBに関するエラッタが存在するそうです。
上記PDFの、これに関すると思われる記述を以下に一部抜粋してみました。
(他にもあるかもしれないです)
さらに詳しいことは、上記PDFを。

※追記
このニュースを否定するニュースが出てきました。
詳しくは下記関連リンクからどうぞ。

MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error
Problem:	A single Data Translation Look Aside Buffer (DTLB) error can incorrectly set the Overflow (bit [62]) in the MCi_Status register. A DTLB error is indicated by MCA error code (bits [15:0]) appearing as binary value, 000x 0000 0001 0100, in the MCi_Status register.
Implication:	Due to this erratum, the Overflow bit in the MCi_Status register may not be an accurate indication of multiple occurrences of DTLB errors. There is no other impact to normal processor functionality.
Workaround:	None identified.
Status:	For the steppings affected, see the Summary Tables of Changes.

Incorrect TLB Translation May Occur After Exit From C6
Problem:	Under certain conditions when C6 and two logical processors on the same core are enabled on a processor, an instruction fetch occurring after a logical processor exits from C6 may incorrectly use the translation lookaside buffer (TLB) address mapping belonging to the other logical processor in the processor core.
Implication:	When this erratum occurs, unpredictable behavior may result.
Workaround:	It is possible for the BIOS to contain a workaround for this erratum.
Status:	For the steppings affected, see the Summary Tables of Changes.

Core C6 May Clear Previously Logged TLB Errors
Problem:	Following an exit from core C6, previously logged TLB (Translation Lookaside Buffer) errors in IA32_MCi_STATUS may be cleared.
Implication:	Due to this erratum, TLB errors logged in the associated machine check bank prior to core C6 entry may be cleared. Provided machine check exceptions are enabled, the machine check exception handler can log any uncorrectable TLB errors prior to core C6 entry. The TLB marks all detected errors as uncorrectable.
Workaround:	As long as machine check exceptions are enabled, the machine check exception handler can log the TLB error prior to core C6 entry. This will ensure the error is logged before it is cleared.
Status:	For the steppings affected, see the Summary Tables of Changes.

Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation
Section 10.9 INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS) of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide will be modified to include the presence of page table structure caches, such as the page directory cache, which Intel processors implement. This information is needed to aid operating systems in managing page table structure invalidations properly.

Intel will update the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide in the coming months. Until that time, an application note, TLBs, Paging-Structure Caches, and Their Invalidation (http://www.intel.com/products/processor/manuals/index.htm), is available which provides more information on the paging structure caches and TLB invalidation.

In rare instances, improper TLB invalidation may result in unpredictable system behavior, such as system hangs or incorrect data. Developers of operating systems should take this documentation into account when designing TLB invalidation algorithms. For the processors affected, Intel has provided a recommended update to system and BIOS vendors to incorporate into their BIOS to resolve this issue.

【関連】
・Core i7のTLBに関するエラッタの報道は間違いらしい